Scaling of Stacked gate technology for embedded NVM

Scaling limitations on NVM Stacked gate embedded into high-performance (HP) CMOS logic process will be reviewed with potential solutions identified. As technology continues its shrink path into 65 nm and beyond, scaling is becoming challenged due to the required high fields for write and erase (W/E) in stacked gate technology and the low leakage requirements for long term retention after cycling (RAC) problems. These requirements are imposing fundamental scaling limitations on the cell design as well as dielectrics thicknesses. These challenges require novel innovations to overcome and extend the viability of stacked gate technology to at least the 45 nm node.