Title :
Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design
Author :
Oh, Saeroonter ; Park, Jeongha ; Wong, S. Simon ; Wong, H. -S Philip
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
A compact model of III-V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22 nm technology III-V SRAM circuit design via III-V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III-V PMOS strength for SRAM to be viable.
Keywords :
III-V semiconductors; MOSFET; SRAM chips; high electron mobility transistors; integrated circuit design; logic circuits; logic design; nanotechnology; 6T-SRAM cell; HFET; III-V logic FET; MOSFET; PMOS device; SRAM cell design; digital logic circuit; high-k dielectric; size 22 nm; Circuit synthesis; FETs; HEMTs; III-V semiconductor materials; Logic circuits; Logic design; Logic devices; MODFETs; MOSFETs; Random access memory; III–V; SRAM; digital logic; gate leakage current; high performance PMOS; parasitic capacitance;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450553
