DocumentCode :
2146686
Title :
Buffer layer dependence of B3.15Nd0.85Ti3O12 (BNdT) based MFIS capacitor for FeFET application
Author :
Luo, Yafeng ; Xie, Dan ; Zang, Yongyuan ; Song, Rui ; Ren, Tianling ; Liu, Litian
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
865
Lastpage :
868
Abstract :
Ferroelectric B3.15Nd0.85Ti3O12 (BNdT) thin films were deposited on SrTiO3/Si, HfO2/Si and Si substrates respectively by sol-gel process. The electrical properties were studied for Metal-Ferroelectric-Semiconductor (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) capacitors. The MFIS structure exhibited well clockwise capacitance-voltage hysteresis loops due to the ferroelectric polarization of BNdT thin film achieved. The maximum memory windows were 3.2 V and 4.7 V, respectively for BNdT deposited on SrTiO3 and on HfO2 buffer layers. In comparison, the memory window of the thin film on Si substrate was 2.8 V. The leakage current of the structure with a buffer layer was much lower than that without a buffer layer. The leakage current of the thin film deposited on SrTiO3/Si was of the order of 10-9-10-8 A/cm2. The electrical properties of the MFIS structures were improved. The results show that the BNdT based MFIS capacitor is a promising candidate for ferroelectric field effect transistor (FeFET).
Keywords :
MFIS structures; boron compounds; buffer layers; dielectric hysteresis; dielectric polarisation; ferroelectric capacitors; ferroelectric thin films; field effect transistors; neodymium compounds; silicon; sol-gel processing; strontium compounds; thick film capacitors; B3.15Nd0.85Ti3O12; FeFET application; HfO2-Si; MFIS capacitor; SrTiO3-Si; buffer layer; capacitance-voltage hysteresis loops; electrical property; ferroelectric field effect transistor; ferroelectric polarization; ferroelectric thin films; leakage current; memory windows; metal-ferroelectric-insulator-semiconductor capacitor; metal-ferroelectric-semiconductor capacitor; sol-gel process; voltage 2.8 V; voltage 3.2 V; voltage 4.7 V; Buffer layers; Capacitors; Ferroelectric materials; Hafnium oxide; Leakage current; Magnetic field induced strain; Neodymium; Semiconductor thin films; Sputtering; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4734680
Filename :
4734680
Link To Document :
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