Analysis of thermally-enhanced SOIC packages

The thermal performance of a number of thermally-enhanced SOIC (Small Outline Integrated Circuit) designs is evaluated by means of a thermal model utilizing Finite Element Analysis (FEA) and compared to that of a standard design. A number of enhancements are explored: reduced pad-inner lead tip spacing, fused leads, and padless “chip-on-lead” construction, and heat slugs. In most of these cases the impact of replacing the standard epoxy molding compound (MC) with a thermally-enhanced molding compound was investigated. A mathematical technique is demonstrated whereby the die (junction) temperature can be calculated at an arbitrary number of power levels and values of air velocity using the results of a small number of FEA solutions. This technique is particularly efficient when dealing with non-linear boundary conditions involving buoyancy-driven convection and radiation. The predictions of the model were verified for one package type and shown to be in good agreement with experiment