DocumentCode :
2147796
Title :
Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations
Author :
Morita, Yusuke ; Mori, Takayoshi ; Migita, S. ; Mizubayashi, W. ; Tanabe, A. ; Fukuda, Kenji ; Matsukawa, T. ; Endo, Kazuhiro ; O´uchi, S. ; Liu, Y.X. ; Masahara, M. ; Ota, Hiroyuki
Author_Institution :
Green Nanoelectron. Center (GNC), Nanoelectron. Res. Inst. Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST) Tsukuba West SCR, Tsukuba, Japan
fYear :
2013
fDate :
16-20 Sept. 2013
Firstpage :
45
Lastpage :
48
Abstract :
The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.
Keywords :
field effect transistors; semiconductor device models; tunnelling; TFET; band-to-band tunneling; channel configurations; distributed-element circuit model; drain current; gate electric field; gate insulators; heavily doped source wells; modified gate configuration; parallel electric field tunnel FET; parallel electric field tunnel field-effect transistors; parallel-plate tunnel capacitor; self-voltage-drop effect; ultrathin channel layer; Capacitors; Electric fields; Epitaxial growth; Logic gates; Resistance; Silicon-on-insulator; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the European
Conference_Location :
Bucharest
Type :
conf
DOI :
10.1109/ESSDERC.2013.6818815
Filename :
6818815
Link To Document :
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