DocumentCode :
2147811
Title :
On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices
Author :
Revelant, A. ; Palestri, Pierpaolo ; Osgnach, Patrik ; Lizzit, Daniel ; Selmi, Luca
Author_Institution :
DIEGM, Univ. degli Studi di Udine, Udine, Italy
fYear :
2013
fDate :
16-20 Sept. 2013
Firstpage :
49
Lastpage :
52
Abstract :
We investigate the operation and performance of planar SiGe/Si and In0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET (TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the hetero-junction and the metallurgical junction is beneficial to improve ION but for the considered devices the ON-current at VDD=0.5V and IoFF=1pA/μm hardly exceeds 1μA/μm. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems.
Keywords :
Ge-Si alloys; III-V semiconductors; gallium arsenide; high electron mobility transistors; indium; indium compounds; silicon; silicon-on-insulator; tunnel transistors; In0.53Ga0.47As-In0.7Ga0.3As-In0.53Ga0.47As; SiGe-Si; heterojunction semiconductor-on-insulator; heterojunction tunnel FET devices; highest on-current; lowest subthreshold swing; semiconductor device optimization; tunnel field effect transistor; Computational modeling; Junctions; Logic gates; Photonic band gap; Silicon; Silicon germanium; Strain;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the European
Conference_Location :
Bucharest
Type :
conf
DOI :
10.1109/ESSDERC.2013.6818816
Filename :
6818816
Link To Document :
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