Complementary n- and p-type TFETs on the same InAs/Al0.05Ga0.95Sb platform

Author

Baravelli, E. ; Gnani, Elena ; Grassi, Roberto ; Gnudi, A. ; Reggiani, S. ; Baccarani, G.

Author_Institution

ARCES & DEIS, Univ. of Bologna, Bologna, Italy

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

69

Lastpage

72

Abstract

Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al_0.05Ga_0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.

Keywords

III-V semiconductors; aluminium compounds; field effect transistors; gallium compounds; indium compounds; low-power electronics; semiconductor heterojunctions; tunnel transistors; 3D simulations; InAs-Al_0.05Ga_0.95Sb; LSTP scenarios; TFET pair; average subthreshold slopes; compatible off-currents; complementary n-type TFETs; complementary p-type TFETs; feasible aspect ratios; full-quantum simulations; heterojunction tunnel field-effect transistors; low operating power; low standby power scenarios; reduced cross section; size 10 nm; size 7 nm; voltage 0.4 V; Aluminum oxide; Dielectrics; Doping; Heterojunctions; Logic gates; Materials; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the European

Conference_Location

Bucharest

Type

conf

DOI

10.1109/ESSDERC.2013.6818821

Filename

6818821