Full-band simulation of p-type ultra-scaled silicon nanowire transistors

We present in this paper a computationally efficient full-band approach to simulate the current characteristics of p-type ultra-scaled, circular, gate-all-around nanowire field-effect transistors (FETs). It is based on an extension of the semiclassical top-of-the-barrier model where tunneling is accounted for through the Wentzel-Kramers-Brillouin approximation and Poisson equation is reduced to a one-dimensional (1-D) problem. As compared to 3-D, full-band, and atomistic simulations, the computational times significantly decrease while still offering accurate device characteristics. The properties of p-type Si nanowire FETs with different crystal orientations, diameters (4-8 nm), and gate lengths (5-15 nm) are calculated as an illustration. It is found that the performance advantage of 〈110〉-oriented devices at relatively long gate lengths - thanks to a lighter transport effective mass than 〈111〉 and 〈100〉 - vanishes at short gate lengths due to an increase of the source-to-drain tunneling rate.