Process challenges in CMOS FEOL for 32nm node

Author

Wang, Guohua ; Wu, Hanming

Author_Institution

Semicond. Manuf. Int. Corp. (SMIC), Beijing, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1134

Lastpage

1137

Abstract

With the navigation of ITRS, 32 nm technology node will be introduced around 2009. Scaling of CMOS devices from 45 nm to 32 nm node has come across significant barriers. In order to overcome these pitch-scaling induced barriers, it is demanded to integrate the most advanced process technologies into the product manufacturing. This paper will review and discuss new technology applications, which would be potentially integrated into the front end of line (FEOL) of 32 nm node. Some examples are discussed in the following areas: double patterning, direct silicon bonding (DSB), hybrid orientation substrate technology, metal/high-K (MHK) gate stacks, stress technologies and ultra-shallow junction (USJ).

Keywords

CMOS integrated circuits; CMOS devices; direct silicon bonding; double patterning; front end of line; hybrid orientation substrate technology; metal-high-K gate stacks; pitch-scaling induced barrier; size 45 nm to 32 nm; stress technologies; ultra-shallow junction; Bonding; CMOS process; CMOS technology; High K dielectric materials; High-K gate dielectrics; Hybrid junctions; Manufacturing processes; Navigation; Silicon; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734749

Filename

4734749