Title :
Reversible logic synthesis of k-input, m-output lookup tables
Author :
Shafaei, Alireza ; Saeedi, Mehdi ; Pedram, Massoud
Author_Institution :
Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
Abstract :
Improving circuit realization of known quantum algorithms by CAD techniques has benefits for quantum experimentalists. In this paper, we address the problem of synthesizing a given k-input, m-output lookup table (LUT) by a reversible circuit. This problem has interesting applications in the famous Shor´s number-factoring algorithm and in quantum walk on sparse graphs. For LUT synthesis, our approach targets the number of control lines in multiple-control Toffoli gates to reduce synthesis cost. To achieve this, we propose a multi-level optimization technique for reversible circuits to benefit from shared cofactors. To reuse output qubits and/or zero-initialized ancillae, we un-compute intermediate cofactors. Our experiments reveal that the proposed LUT synthesis has a significant impact on reducing the size of modular exponentiation circuits for Shor´s quantum factoring algorithm, oracle circuits in quantum walk on sparse graphs, and the well-known MCNC benchmarks.
Keywords :
Benchmark testing; Computers; Logic gates; Quantum computing; Registers; Table lookup; Welding; Binary welded tree; Logic synthesis; Lookup tables; Reversible circuits; Shor´s quantum number-factoring algorithm;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference_Location :
Grenoble, France
Print_ISBN :
978-1-4673-5071-6
DOI :
10.7873/DATE.2013.256