Novel low temperature 3D wafer stacking technology for high density device integration

Author

Radu, Iuliana ; Gaudin, G. ; Van Den Daele, W. ; Letertre, F. ; Mazure, C. ; Di Cioccio, L. ; Lacave, T. ; Mazen, F. ; Scheiblin, P. ; Signamarcheix, Thomas ; Cristoloveanu, S.

Author_Institution

SOITEC, Bernin, France

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

151

Lastpage

154

Abstract

Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart Cut™ technology and solid phase re-crystallization. Thin silicon PN bi-layers of high quality are transferred onto new handle substrate without exceeding 500°C. The current-voltage characteristics of the intrinsic PN diode are significantly improved by using low temperature solid-phase epitaxial re-growth process in combination with the Smart Cut™ technology. An original process integration scheme is described in order to minimize the diode leakage.

Keywords

elemental semiconductors; epitaxial growth; recrystallisation; semiconductor diodes; semiconductor technology; silicon; Si; Smart Cut technology; current-voltage characteristics; diode leakage; handle substrate; intrinsic PN diode; low temperature 3D wafer stacking technology; low temperature solid-phase epitaxial re-growth; process integration; solid phase recrystallization; thin silicon PN bi-layers; very high density device integration; Annealing; Junctions; Silicon; Stacking; Temperature; Temperature measurement; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the European

Conference_Location

Bucharest

Type

conf

DOI

10.1109/ESSDERC.2013.6818841

Filename

6818841