STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process

As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using “gate-last” process (Replacement Gate - RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (μA/μm) (-16%) once compared to transistors without eSiGe (-7%).