DocumentCode :
2148713
Title :
Reverse engineering digital circuits using functional analysis
Author :
Subramanyan, Pramod ; Tsiskaridze, Nestan ; Pasricha, Kanika ; Reisman, Dillon ; Susnea, Adriana ; Malik, Sharad
Author_Institution :
Departments of Electrical Engineering and Computer Science, Princeton University, USA
fYear :
2013
fDate :
18-22 March 2013
Firstpage :
1277
Lastpage :
1280
Abstract :
Integrated circuits (ICs) are now designed and fabricated in a globalized multi-vendor environment making them vulnerable to malicious design changes, the insertion of hardware trojans/malware and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders and subtracters. Our techniques require no manual intervention and experiments show that they determine the functionality of more than 51% and up to 93% of the gates in each of the practical test circuits that we examine.
Keywords :
Algorithm design and analysis; Latches; Logic gates; Radiation detectors; Random access memory; Reverse engineering; Shift registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference_Location :
Grenoble, France
ISSN :
1530-1591
Print_ISBN :
978-1-4673-5071-6
Type :
conf
DOI :
10.7873/DATE.2013.264
Filename :
6513710
Link To Document :
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