DocumentCode :
2148810
Title :
Investigation of SRAM using BTI-aware statistical compact models
Author :
Jie Ding ; Reid, Dave ; Millar, C. ; Asenov, Asen
Author_Institution :
Device Modelling Group, Univ. of Glasgow, Glasgow, UK
fYear :
2013
fDate :
16-20 Sept. 2013
Firstpage :
186
Lastpage :
189
Abstract :
In this paper, statistical variability and different levels of BTI degradation are introduced into a compact model by statistical parameter extraction. Static Random Access Memory (SRAM) is used to test the compact model and to investigate the effects of MOSFET statistical variability and degradation at circuit level. Statistical distributions of Static Noise Margin (SNM) under different scenarios representing various degradation levels as well as mismatch levels between `on´ and the rest of the SRAM cell transistors are compared to investigate their impacts on SRAM stability. A surface response model of the dependence of the mean and standard deviation of SNM on circuit ageing and transient stress is also developed to quickly evaluate SRAM stability at arbitrary degradation levels.
Keywords :
MOSFET; SRAM chips; integrated circuit reliability; integrated circuit testing; statistical analysis; BTI degradation; MOSFET statistical variability; SRAM; circuit ageing; static noise margin; static random access memory; statistical compact models; statistical parameter extraction; surface response model; transient stress; Circuit stability; Degradation; Integrated circuit modeling; SRAM cells; Stability analysis; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the European
Conference_Location :
Bucharest
Type :
conf
DOI :
10.1109/ESSDERC.2013.6818850
Filename :
6818850
Link To Document :
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