• DocumentCode
    2149155
  • Title

    Integrate LaOx-capping layer into metal gated CMOS devices using a gate-first approach for sub-45nm technology node and the device reliability thereof

  • Author

    Hongyu Yu ; Chang, S.Z. ; Kubicek, S. ; Schram, T. ; Wang, X.P. ; Biesemans, S.

  • Author_Institution
    Sch. of EEE, Nanyang Technol. Univ., Singapore, Singapore
  • fYear
    2008
  • fDate
    20-23 Oct. 2008
  • Firstpage
    1260
  • Lastpage
    1263
  • Abstract
    This paper provides a comprehensive study on the integration of LaOx capping layer for sub-45 nm metal gated CMOS devices with Hf-based high-K dielectrics in a gate first manner. Two different integration routes, i.e. Dual Metal Dual Dielectric flow (DMDD) and Single Metal Dual Dielectric (SMDD) flow, are reported and compared. The device reliability study is also provided.
  • Keywords
    CMOS integrated circuits; lanthanum compounds; Hf-based high-K dielectrics; capping layer; device reliability; metal gated CMOS devices; single metal dual dielectric flow; sub-45nm technology node; Annealing; CMOS technology; Electrodes; Fabrication; High-K gate dielectrics; MOCVD; MOS devices; Power lasers; Random access memory; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-2185-5
  • Electronic_ISBN
    978-1-4244-2186-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2008.4734780
  • Filename
    4734780
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2149155