TCAD application in process optimization to reduce source/drain junction capacitance of PMOS transistor in the development of 65nm low leakage technology

In this paper, technology computer aided design (TCAD) was applied to optimize the fabrication process to reduce the parasitic capacitance of PMOS transistor at the source/drian (S/D) junction (Cj) in developing the 65 nm low leakage (65 nmLL) technology. It was found that Cj can be effectively reduced by combining relative high-energy well implant and proper threshold voltage (Vt) implant method. Through measured data and TCAD simulation, this paper also demonstrates a ¿doping compensation effect¿ by tuning Vt and Halo implants with proper species, energy, and dosage, to achieve the Cj reduction.