Title :
A three-level wiring capacitance analysis for VLSIs using a three-dimensional simulator
Author :
Ushiku, Y. ; Ono, H. ; Shigyo, N.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A three-dimensional simulator has been developed for calculating the capacitance values for three-level interconnections. This simulator has been proved to be sufficiently effective and exact by comparisons between simulation results and actual measurement. In the case of three-level interconnections, compared with the single-level interconnection case, the cross-wiring capacitance values were larger and the adjacent wiring capacitance values were smaller. The necessity for a simulator which can handle more than four-level interconnections is discussed. Some scaling effects are also considered.<>
Keywords :
VLSI; capacitance; circuit analysis computing; metallisation; VLSI; adjacent wiring capacitance; cross-wiring capacitance; scaling effects; three-dimensional simulator; three-level interconnections; three-level wiring capacitance analysis; Analytical models; Capacitance; Circuit simulation; Delay estimation; Insulation; Integrated circuit interconnections; Scanning electron microscopy; Shape measurement; Very large scale integration; Wiring;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32826
