Title :
A PVT insensitive field programmable gate array time-to-digital converter
Author :
Poki Chen ; Hsiu Che Cheng ; Widodo, Achmad ; Wei Xiang Tsai
Abstract :
A process, voltage and temperature (PVT) insensitive time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) is presented. The aim is to provide a PVT insensitive TDC solution with god enough resolution and wide measurement range. With the aid of FPGA embedded phase locked loop (PLL) which provides eight different output phases, a constant resolution around 84 ps can be ensured. The short term differential nonlinearity (DNL) is measured to be -0.482 ~ 0.457 LSB, and the corresponding integral nonlinearity (INL) is merely -0.612 ~ 0.575 LSB. This TDC was tested to be fully functional over 0°C to 50°C ambient temperature ranges with extremely low variation on resolution.
Keywords :
field programmable gate arrays; phase locked loops; time-digital conversion; DNL; FPGA; INL; PLL; PVT insensitive TDC solution; PVT insensitive field programmable gate array; differential nonlinearity; integral nonlinearity; phase locked loop; process-voltage-and-temperature insensitivity; temperature 0 C to 50 C; time-to-digital converter; Clocks; Field programmable gate arrays; Image resolution; Measurement uncertainty; Phase locked loops; Temperature measurement; PVT insensitivity; field programmable gate array (FPGA; phase-locked loop (PLL); time-to-digital converter;
Conference_Titel :
Time-to-Digital Converters (NoMe TDC), 2013 IEEE Nordic-Mediterranean Workshop on
Conference_Location :
Perugia
Print_ISBN :
978-1-4799-1184-4
DOI :
10.1109/NoMeTDC.2013.6658232
