Title :
Simulation and measurement of picosecond step responses in VLSI interconnections
Author :
Schreyer, T.A. ; Nishi, Yoshio
Author_Institution :
Appl. Electron. Lab. 2, Stanford, CA, USA
Abstract :
The delays caused by interconnections in VLSI (very large scale integration) integrated circuits are analyzed. The effects of metal resistance and silicon conduction have on signal propagation are examined, modeling the interconnection as a microstrip transmission line over a dual dielectric. The analysis was performed by evaluating the solution of the telegraphers´ equations for this type of transmission line in the frequency domain and then obtaining the line´s step-response numerically by means of an inverse Laplace transform. Analysis of step response computations, with experimental verification, shows that signal propagation in VLSI interconnections can usually be described by quasi-TEM (transverse electromagnetic) propagation, rather than the so-called slow-wave propagation assumed by several authors. In addition, signal degradation due to metal resistance is generally not a problem for metal interconnections up to 1 cm in length.<>
Keywords :
Laplace transforms; VLSI; delays; metallisation; step response; transmission line theory; VLSI interconnections; delays; dual dielectric; frequency domain; inverse Laplace transform; metal resistance; microstrip transmission line; picosecond step responses; quasitransverse EM propagation; signal propagation; silicon conduction; telegraphers´ equations; Circuit simulation; Dielectric measurements; Distributed parameter circuits; Electrical resistance measurement; Electromagnetic propagation; Integrated circuit interconnections; Integrated circuit measurements; Laplace equations; Transmission line measurements; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32827
