264 Channel TDC Platform applying 65 channel high precision (7.2 psRMS) FPGA based TDCs

In this paper the implementation of a 65 channel high precision Time-to-Digital Converter in a single Field Programmable Gate Array (FPGA) is presented. The TDC applies the interpolation method for time measurements. The precision of the TDC is increased with the Wave Union Launcher method. In order to overcome the minimum pulse width limitation a semi-asynchronous pulse stretcher is implemented which has been verified to allow a measurement of a pulse width <; 500 ps. The TDC has a typical precision of 7.2 ps RMS (14 ps RMS on the worst channel) on a single channel. Additionally, the 264 Channel TDC Platform, TDC Readout Board (TRB3), is presented in the paper applying the described TDC.