Optimizing time-to-digital converter architecture for successive approximation time measurements

The paper is focused on the discussion of various variants of time-to-digital converter architectures for successive approximation time measurements (SA-TDC) realized strictly in the time domain. First, the revision of feedforward type architectures presented in previous works is carried out including propositions of optimized configurations that reduce the complexity of hardware blocks. Second, the feedback-based architecture for SA-TDCs is introduced where decisions in each conversion steps is taken by a single digital block. Furthermore, several versions of SA-TDC feedback-based architecture optimized in terms of compensation of logic propagation delays, removing redundancy of programmable delay lines and increasing energy efficiency are proposed.