Three-dimensional impedance engineering for mixed-signal system-on-chip applications

We describe a novel approach for three-dimensional substrate impedance engineering using p^-/p⁺ epi substrate for mixed-signal SoC applications. Highly doped substrate with a thin epitaxial layer is used to prevent latch-up at tight design rules in high performance digital CMOS for beyond 40 GHz applications. Metal vias extending from the chip surface to the p⁺ substrate are used as Faraday cage for EM wave shielding as well as ¿true ground¿ contacts. Self-limiting semi-insulating micro-PS regions are inserted into selected regions of Si substrates from the backside of the wafer. On-chip inductors are situated above the semi-insulating micro-PS regions allowing for greatly increased Q and f_r. Bond pads on micro-PS regions increase the bond pad resonant frequency of up to 56.2 GHz and increase crosstalk isolation between bond pads. These technologies require minimum intrusion to conventional Si CMOS processing, making them practical and yet effective new technologies that offer outstanding improvements with regard to the performance of mixed-signal SoCs. It is an enabling factor for Si ICs to directly challenge the compound semiconductor technologies.