Title :
The method for hardware design to generate NSL from UML diagram and the experiments with FPGA
Author :
Kanou, D. ; Yamazaki, R. ; Shimizu, N.
Author_Institution :
Sch. of Eng., Tokai Univ., Hiratsuka, Japan
Abstract :
In this paper, we present the method for the hardware design. This method generates logic synthesizable HDL from the UML diagram automatically. And, we present the experiments by the use of our method. In the experiments, the undergraduate students design hardware using our method and the other method of the handwriting design.
Keywords :
Unified Modeling Language; field programmable gate arrays; logic design; FPGA; NSL diagram; UML diagram; hardware design method; undergraduate students design hardware; Analytical models; Educational institutions; Field programmable gate arrays; Hardware; Unified modeling language; Vents; FPGA; Hardware design; UML diagram; experiment;
Conference_Titel :
Computing, Electronics and Electrical Technologies (ICCEET), 2012 International Conference on
Conference_Location :
Kumaracoil
Print_ISBN :
978-1-4673-0211-1
DOI :
10.1109/ICCEET.2012.6203755
