Thermal-aware datapath merging for coarse-grained reconfigurable processors

The increased power densities of deep submicron process technologies have made on-chip temperature to become a critical design issue for high-performance integrated circuits. In this paper, we address the datapath merging problem faced during the design of coarse-grained reconfigurable processors from a thermal-aware perspective. Assuming a reconfigurable processor able to execute a sequence of datapath configurations, we formulate and efficiently solve the thermal-aware datapath merging problem as a minimum cost network flow. In addition, we integrate floorplan awareness of the underlying reconfigurable processor guiding the merging decision to account also for the effects of heat diffusion. Extensive experimentation regarding different configuration scenarios, technology nodes and clock frequencies showed that the adoption of the proposed thermal-aware methodology delivers up to 8.27K peak temperature reductions and achieves better temperature flattening in comparison to a low power but thermal-unaware approach.