A 179-mW 2304-bit flexible LDPC decoder for Wireless-MAN applications

Author

Bao, Dan ; Xiang, Bo ; Shen, Rui ; Pan, An ; Chen, Yun ; Zeng, Xiao-Yang

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1625

Lastpage

1628

Abstract

A 2304-bit flexible decoder for low-density parity-check (LDPC) codes is presented for Wireless-MAN applications. Based on modified turbo-decoding message-passing (M-TDMP) algorithm, the decoder achieves low complexity as well as fast convergence which produces high throughput of 138 Mbps working at 50 MHz. By adopting a novel scheme for early termination of iteration, the proposed decoder obtains large power efficiency. The decoder is implemented in SMIC 0.18 Â¿m 1P6M CMOS technology, features a power dissipation of 179-mW operating at 50 MHz, and costs an area of 12.5 mm².

Keywords

CMOS integrated circuits; iterative decoding; message passing; metropolitan area networks; parity check codes; turbo codes; wireless LAN; CMOS technology; bit rate 138 Mbit/s; flexible LDPC decoder; frequency 50 MHz; iterative decoding; power 179 mW; size 0.18 mum; turbo-decoding message-passing; wireless MAN; word length 2304 bit; CMOS technology; Digital video broadcasting; Forward error correction; Iterative algorithms; Iterative decoding; Matrix decomposition; Parity check codes; Power dissipation; Satellite broadcasting; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734861

Filename

4734861