Single ended swing restoring pass transistor cells for logic synthesis and optimization

In this contribution we present three cells in pass transistor logic which can be directly appended to any CMOS standard cell library, and provide improvements in timing, power and area. These cells utilize N-type pass transistor logic and single ended swing restoration as opposed to the dual rail swing restoration in SRPL. The three cells are 2-input exor, 2-input multiplexer and 4-input multiplexer. Circuit simulations indicate an overall delay improvement on all timing arcs compared to traditional CMOS implementations, and in benchmark tests for logic optimization, delay and power were improved by up to 29% and 36%, respectively