A complex BPF with on chip auto-tuning architecture for low-IF receivers

A 3^rd order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 ¿m standard CMOS technology. The complex filter is centered at 4.092 MHz with bandwidth of 2.4 MHz. The in-band 3^rd order harmonic input intercept point (IIP3) is larger than 19 dBm, with 50 ¿ as the source impedance. The input referred noise is about 80 ¿V_rms. The RC tuning is based on binary search algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28×0.22 mm², less than 1/8 of that of the main-filter which is 0.92×0.59 mm². After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6 mA with a 1.8 V power supply.