DocumentCode
2151669
Title
Edge reversal-based asynchronous timing synthesis
Author
Franca, Felipe M G ; Alves, Vladimir C. ; Granja, Edson P.
Author_Institution
COPPE, Univ. Fed. do Rio de Janeiro, Brazil
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
45
Abstract
A synthesis methodology for the production of self-timed versions of digital circuits designed under the synchronous approach is introduced. The methodology is based on Scheduling by Edge Reversal (SER), a very simple and powerful distributed synchronizer. Its correctness is proved and it is shown how, as a result of applying it to a given target (synchronous) circuit, a functionally equivalent asynchronous SER-driven circuit is produced
Keywords
asynchronous circuits; logic design; timing; SER; asynchronous timing synthesis; distributed synchronizer; scheduling by edge reversal; self-timed digital circuit; Circuit synthesis; Clocks; Delay; Digital circuits; Digital systems; Logic gates; Production; Scheduling; Synchronization; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706818
Filename
706818
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