Constraints in p-channel device engineering for submicron CMOS technologies

The device engineering of submicron p-channel devices was studied. The devices analyzed were restricted to n-tub devices in p- on p/sup +/ epi material. Both n/sup +/- and p/sup +/-poly gate devices were evaluated at channel lengths down to 0.4 mu m. It was found that p/sup +/-poly gate devices have superior punchthrough resistance as compared to n/sup +/-poly gate devices, but can suffer from device instability due to boron penetration from the gate into the gate oxide or into the silicon. Novel device structures can be used to make the punchthrough resistance of n/sup +/-poly devices acceptable. Gate-field-induced drain leakage current will become a limiting factor when the gate oxide is scaled to below 100 AA. The degraded vertical isolation of source/drain to substrate in shallow n-tubs will limit the thickness of the p- and p/sup +/ epi layer.<>