A synchronous algorithm of network coding with hardware logic

This paper presents an efficient hardware prototype for network coding (NC). First, a packet synchronization mechanism is introduced to settle the problem of packet arriving mismatch between different incoming channels. Then a high-speed lookup-table-based circuit is designed to perform dot product over Galois Field, which forms the basic calculation unit of NC operation. Taking the speed advantage of FPGA hardware, this prototype is able to perform network coding operations within several hundred nanoseconds. Thus further studies and emulations on NC are able to be carried out upon this platform in the real network scenario.