A novel DCPLL with small-area and low-power DCO for SoC applications

Author

Juan, Chen ; Shou-hai, Fang ; Xin, Chen

Author_Institution

Coll. of Inf. Sci. & Eng., Nanjing Univ. of Technol., Nanjing, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1867

Lastpage

1870

Abstract

This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method, a high performance of DCO can be implemented in a straightforward way. Finally, the DCPLL design is implemented by SMIC 0.18 Â¿m logic 1P6M CMOS technology. The area of the DCPLL is 0.08 mm². The post-layout simulation results by Spice show that the frequency range of the digitally controlled oscillator (DCO) is from 96 MHz to 542.5 MHz and the resolution of the DCO is about 22 ps. The power consumption of the DCPLL is 6.14 mW when the DCO operates at 400 MHz.

Keywords

CMOS logic circuits; phase locked loops; phase locked oscillators; system-on-chip; DCPLL; SMIC; SoC applications; digitally controlled oscillator; digitally controlled phase locked loop; frequency 400 MHz; frequency 542.5 MHz; frequency 96 MHz; logic 1P6M CMOS technology; low power DCO; power 6.14 mW; small area DCO; Circuit noise; Circuit optimization; Clocks; Delay; Digital control; Frequency; Hardware design languages; Phase locked loops; Voltage-controlled oscillators; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734922

Filename

4734922