A CMOS quaternary-to-binary logic decoder

Author

Kim, Jeong Beom

Author_Institution

Dept. of Electron. Eng., Kangwon Nat. Univ., South Korea

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1874

Lastpage

1876

Abstract

This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.

Keywords

CMOS logic circuits; SPICE; circuit reliability; decoding; multivalued logic circuits; CMOS circuits; HSPICE; current-mode multiple-valued logic; power-delay-product reduction; quaternary-to-binary logic decoder; reliability; voltage 2.5 V; CMOS logic circuits; CMOS technology; Decoding; Integrated circuit interconnections; Inverters; Logic circuits; Logic devices; Signal generators; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734924

Filename

4734924

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2152820