DocumentCode
2152843
Title
Distributed shared memory architecture for JUMP-1 a general-purpose MPP prototype
Author
Matsumoto, Takashi ; Kudoh, Tomohiro ; Nishimura, Katsunobu ; Hiraki, Kei ; Amano, Hideharu ; Tanaka, Hidehiko
Author_Institution
Tokyo Univ., Japan
fYear
1996
fDate
12-14 Jun 1996
Firstpage
131
Lastpage
137
Abstract
We describe and evaluate a novel distributed-shared memory (DSM) architecture of JUMP-1, a general-purpose MPP system. For improving performance, JUMP-1 DSM architecture utilizes cooperation of the network, construction of memory-directories and a memory-protocol that unifies memory-consistency, communication and synchronization. Among features of JUMP-1 DSM, we show details of Reduced Hierarchical Bit-map Directory schemes (RHBDs) which utilize hierarchy embedded in the interconnection network for reducing network traffic on shared memory operations. Three variations of the RHBD are implemented on a network called the RDT (Recursive Diagonal Torus) consisting of the hierarchical structure of two-dimensional tori. In RHBDs, the bit map directory is reduced for quick multicasting without accessing the directory in each hierarchy. Most unnecessary packets caused by reduction of the bit map are removed with the pruning cache provided in the router. The results of simulation demonstrate that latency for cache coherent messages is much improved compared with traditional directory schemes
Keywords
distributed memory systems; memory architecture; multiprocessor interconnection networks; parallel architectures; shared memory systems; DSM architecture; JUMP-1; MPP prototype; Recursive Diagonal Torus; Reduced Hierarchical Bit-map Directory; architecture; cache coherent messages; distributed-shared memory; interconnection network; multicasting; pruning cache; two-dimensional tori; Access protocols; Communication system traffic control; Delay; Design engineering; Hardware; Memory architecture; Memory management; Multiprocessor interconnection networks; Parallel processing; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures, Algorithms, and Networks, 1996. Proceedings., Second International Symposium on
Conference_Location
Beijing
ISSN
1087-4089
Print_ISBN
0-8186-7460-1
Type
conf
DOI
10.1109/ISPAN.1996.508972
Filename
508972
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