A multi-core/multi-chip scalable architecture of associative processors employing bell-shaped analog matching cells

A methodology for building a low-power high-capacity associative system has been developed. In the system, matching cells having bell-shaped I-V characteristics play the role of similarity-evaluation elements and can be replaced by nanoscale quantum-effect devices. The study is aiming to extend the current CMOS designs to the coming era of nano-devices. A multi-core/multi-chip architecture has been developed in a 0.18 ¿m standard CMOS technology. The system is scalable to adapt to the vast-scale integration capacity provided by nanoscale devices. Solutions to the problems of device characteristics variability and signal propagation delay in inter-chip interconnects have been developed in the study.