Design and performance analysis of one 32-bit dual issue RISC processor for embedded application

Author

Huang, Xiaoping ; Fan, Xiaoya ; Zhang, Shengbing

Author_Institution

Comput. Acad., Northwestern Polytech. Univ., Xi´´an, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1827

Lastpage

1830

Abstract

One 32-bit RISC processor for embedded application is presented. With respect to the limitation of power and area in the embedded system, the RISC processor is deliberately designed. Dual-issue technology is adopted to improve the performance; the complex logic of the dynamic scheduling algorithm is allocated into different pipeline stage to improve the frequency. Lower power design method is used to decrease the whole power. The processor is implemented by SMIC 0.18 um CMOS technology. It contains almost 5 million transistors; the core frequency is 266 MHz and the power is about 1.3 w under it. The embedded VxWorks OS can run on it stably. The performance analysis of the RISC processor is also provided. According to the embedded benchmark program, the average IPC of the RISC processor is nearly 1.5.

Keywords

CMOS integrated circuits; dynamic scheduling; low-power electronics; microprocessor chips; processor scheduling; reduced instruction set computing; CMOS technology; RISC processor; core frequency; dynamic scheduling; embedded application; frequency 266 MHz; lower power design; performance analysis; CMOS logic circuits; CMOS technology; Dynamic scheduling; Embedded system; Heuristic algorithms; Performance analysis; Pipelines; Process design; Reduced instruction set computing; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734935

Filename

4734935