Analog/RF design techniques for high performance nanoelectronic on-chip interconnects

On-chip interconnects form the bottleneck of VLSI system performance. As technology progresses, VLSI on-chip interconnects encounter increasingly significant challenges, such as (1) signal attenuation and (2) crosstalk coupling. This paper proposes two analog/RF design techniques for high performance nanoelectronic on-chip interconnects: (1) application of distributed amplifiers for signal attenuation compensation by reducing interconnect effective resistance, and (2) application of bandpass filters for noise immunity in a frequency separated VLSI on-chip communication system. HSPICE-RF simulation results in 65 nm CMOS technology verify that the proposed analog/RF design techniques achieve improved performance and reliability for high performance nanoelectronic on-chip interconnects.