A core-based multi-function security processor with GALS Wrapper

The security processor proposed in this paper is composed by multiple cryptographic cores. And due to the use of embedded DMA and data burst transfer, the processor can act as a bus master. This architecture improves the efficiency of system bus and reduces the burden of host CPU. Additionally, the proposed processor is connected to the system bus via a GALS Wrapper. Thus, high throughput can be achieved by using faster clock than the host CPU utilizes. On the other hand, the clock of the security processor can also be slowed down if the low power application is desired.