New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

Author

Momodomi, M. ; Kirisawa, R. ; Nakayama, R. ; Aritome, S. ; Endoh, T. ; Itoh, Y. ; Iwata, Y. ; Oodaira, H. ; Tanaka, T. ; Chiba, M. ; Shirota, R. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

412

Lastpage

415

Abstract

Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0- mu m design rules, the unit cell area per bit is 12.9- mu m/sup 2/, which is small enough to realize a 4-Mb EEPROM.<>

Keywords

CMOS integrated circuits; EPROM; NAND circuits; integrated memory circuits; 1 micron; 4 Mbit; 5 V; EEPROM; NAND structure cell; design rules; high-voltage CMOS process; programming sequence; reliability; reliable programming characteristics; unit cell area; unselected bit lines; wide threshold margin; CMOS process; CMOS technology; EPROM; Magnetic memory; Power supplies; Pulsed power supplies; Solid state circuits; Threshold voltage; Tunneling; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32843

Filename

32843