Title :
Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays
Author :
Hasan, Shehzad ; Palit, Ajoy K. ; Anheier, Walter
Author_Institution :
ITEM/FB1, Univ. of Bremen, Bremen
Abstract :
Noise effects due to parasitic couplings between two closely located neighboring wires have significant impact on the performance of the DSM chips. Analysis of a single wire with all its couplings is required to find out the maximum effect of the crosstalk noise both in terms of glitch and delay. This paper introduces a decoupled RLGC transient model for victim wire which is highly accurate and flexible. This model can be used to compute the maximum delay and glitch effect due to crosstalk on a victim wire under different slew rates and delays of aggressor and victim signals. The equivalent victim model´s accuracy is validated by the PSPICE simulation results and yet the simulation speed is at least 13 times faster than the latter.
Keywords :
SPICE; equivalent circuits; integrated circuit interconnections; integrated circuit noise; PSPICE simulation; coupled interconnects; crosstalk induced glitches; delays; equivalent circuit; noise effects; parasitic couplings; Capacitance; Computational modeling; Crosstalk; Delay effects; Inductance; Integrated circuit interconnections; Mutual coupling; SPICE; Voltage; Wire;
Conference_Titel :
Signal Propagation on Interconnects, 2009. SPI '09. IEEE Workshop on
Conference_Location :
Strasbourg
Print_ISBN :
978-1-4244-4490-8
Electronic_ISBN :
978-1-4244-4489-2
DOI :
10.1109/SPI.2009.5089850