• DocumentCode
    2153861
  • Title

    Formal verification of the MetaH executive using linear hybrid automata

  • Author

    Vestal, Steve

  • Author_Institution
    Honeywell Technol. Center, Minneapolis, MN, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    134
  • Lastpage
    144
  • Abstract
    MetaH is a language and toolset for the development of real time high assurance software. There is an associated executive that is automatically configured by the tools to perform the task and message scheduling specified for an application. Linear hybrid automata are finite state automata augmented with real-valued variables. Transitions between discrete states may be conditional on the values of these variables and may reassign variables. These variables can be used to model real time and accumulated task compute time as well as program variables. We developed a concurrent linear hybrid automata model for that portion of the MetaH executive software that implements task scheduling and time partitioning. A reachability analysis was performed to verify selected properties for a selected set of application configurations. The approach combines aspects of testing and verification and automates much of the modeling and analysis. There are limits on the degree of assurance that can be provided, but the approach may be more thorough and less expensive than some traditional testing methods
  • Keywords
    finite state machines; formal verification; message passing; reachability analysis; real-time systems; software reliability; software tools; supervisory programs; MetaH executive; MetaH language; accumulated task compute time; application configurations; concurrent linear hybrid automata model; discrete states; executive software; finite state automata; formal verification; linear hybrid automata; message scheduling; program variables; reachability analysis; real time high assurance software development; real-valued variables; task scheduling; time partitioning; Application software; Automata; Automatic testing; Formal verification; Hardware; Performance analysis; Processor scheduling; Reachability analysis; Real time systems; Software tools;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real-Time Technology and Applications Symposium, 2000. RTAS 2000. Proceedings. Sixth IEEE
  • Conference_Location
    Washington, DC
  • ISSN
    1080-1812
  • Print_ISBN
    0-7695-0713-1
  • Type

    conf

  • DOI
    10.1109/RTTAS.2000.852458
  • Filename
    852458