Mixed signal op-amp in 65nm technology

Author

Chandekar, Omini ; Kharbikar, Tushar ; Palsodkar, P.P. ; Dakhole, P.K.

Author_Institution

Yeshwantrao Chavan Coll. of Eng., Nagpur, India

fYear

2012

fDate

21-22 March 2012

Firstpage

615

Lastpage

619

Abstract

This paper presents a new methodology for design of high speed CMOS operational amplifier in Sub-micron region. The op-amp uses a compensation technique which increases the unity gain frequency and phase margin simultaneously. The CMOS op-amp presented in this paper works on 1.5V designed in 65nm standard CMOS technology. It exhibits 86dB DC gain. With load of 5pF, the unity gain frequency and phase margin are 34MHz and 84° respectively. The op-amp is fairly small and slew rate is more than other low power low voltage op-amps reported. This op-amp is then simulated for application in peak detector.

Keywords

CMOS integrated circuits; electric potential; mixed analogue-digital integrated circuits; operational amplifiers; DC gain; compensation technique; high speed CMOS operational amplifier; low power low voltage op-amps; mixed signal op-amp; peak detector; phase margin simultaneously; sub-micron region; unity gain frequency; voltage 1.5 V; wavelength 65 nm; CMOS integrated circuits; CMOS technology; Noise; Advanced Design System (ADS); Compensation technique; OTA; deep sub-micron;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Electronics and Electrical Technologies (ICCEET), 2012 International Conference on

Conference_Location

Kumaracoil

Print_ISBN

978-1-4673-0211-1

Type

conf

DOI

10.1109/ICCEET.2012.6203892

Filename

6203892