Integral power net integrity analysis of a packaged u-Controller system including the u-Controller on-chip power net distribution

In this paper an application of Integral Analysis Techniques is demonstrated for determining the effect of large simultaneously switching IC Circuit Groups (internal IC-Circuits and I/O´s ) on their Power Integrity (PI) and I/O-Signal Integrity (I/O-SI) behavior. The analysis includes the complex Packaging (CP+PCB). A large u-Controller and its wire-bonded Chip-Package(CP) plus its Test-PCB have been used for our study, which is in this paper focused on the analysis of Conducted Power Emission Noise in Frequency- and Time-Domain (FD, TD). The FD-power analysis results are shown in comparison with related Spectrum Analyzer measurements. The methodology can analogously be applied to conducted I/O Signal Noise. The achieved short CPU run times and the ease-of- use are underlined.