Performance evaluation of FPGA based crossbar NoC architecture

With the development of IC technology, the commutation architecture has become a major bottleneck in Multi-processor System on Chip (MPSoC) design, which imposes communication based design into computation based design. It must provide enough bandwidth as well as the latency requirement. Network on Chip (NoC) has been considered as a new paradigm for its extensibility and power efficiency. This paper concentrated on the scalability issue based on an in-house developed crossbar NoC, which consisted of fully connected channels for every pair of processors through transmitter, receiver and links. The major contributions are the following: implemented the NoC prototyped on FPGA with extended processor number from 4 to 6, evaluated the whole chip performance on pipelined-matrix-multiplication (PMM) benchmark and analyzed the scalability of the crossbar NoC in terms of area and performance. The experimental results showed the maximum speedup of 4.730 in the PMM benchmark and a small area overhead less than 3.1%.