DocumentCode
2154124
Title
Towards supply-grid-based derating of timing margins
Author
Svensson, Lars J. ; Pihl, Johnny ; Andersson, Daniel A. ; Nilsson, Björn ; Larsson-Edefors, Per
Author_Institution
Dept of Comput. Sci. & Eng., Chalmers Univ. of Technol., Gothenburg
fYear
2009
fDate
12-15 May 2009
Firstpage
1
Lastpage
2
Abstract
We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spatial map of the supply voltage waveforms. We relate these waveforms to the expected excess logic delays, and estimate the required derating of the critical setup paths.
Keywords
microprocessor chips; power supply circuits; timing; critical setup path; logic delays; processor chip; supply voltage network; supply-grid-based derating; timing margins; word length 32 bit; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Propagation on Interconnects, 2009. SPI '09. IEEE Workshop on
Conference_Location
Strasbourg
Print_ISBN
978-1-4244-4490-8
Electronic_ISBN
978-1-4244-4489-2
Type
conf
DOI
10.1109/SPI.2009.5089868
Filename
5089868
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