Soft error stability of p-well versus n-well CMOS latches derived from 2-D transient simulations

Author

Weaver, H.T.

Author_Institution

Sandia Nat. Lab., Albuquerque, NM, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

512

Lastpage

515

Abstract

Numerical simulations for the response of inverters to high-energy ion strikes are used to compare the single-event-upset (SEU) hardness of p- versus n-well technologies. A constant-geometry, mirror-image technique is used to generate the technology designs, with the objective of presenting features inherent to the well type. The p-well exhibits better SEU tolerance at low ion energies, but in the high-energy regime the two technologies become essentially equivalent. This results from saturation effects known to occur in modern SRAMs (static random access memories).<>

Keywords

CMOS integrated circuits; VLSI; digital simulation; integrated circuit technology; integrated memory circuits; random-access storage; semiconductor device models; 2-D transient simulations; SEU; SEU tolerance; SRAMs; constant-geometry; high ion energies; high-energy ion strikes; low ion energies; mirror-image technique; n-well CMOS latches; p-well CMOS latches; response of inverters; saturation effects; single event upset hardness; soft error stability; static random access memories; CMOS technology; Doping; Feedback circuits; Geometry; Inverters; Latches; Mirrors; Single event upset; Stability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32867

Filename

32867