A novel FPGA manufacture-oriented interconnect fault test

This paper presents a novel build-in-self-test (BIST) manufacture-oriented interconnect test strategy of SRAM-based field programmable gate arrays (FPGA). Programmable switches (PSs) and line segments are tested separately, which is different from previous methods. An improved depth-first-search (DFS) algorithm is developed for automatically deriving minimal or near minimal test configuration patterns for switch matrix (SM) test. Switch stuck-off, stuck-on faults and line open, short and bridging faults are covered. The experiment on Xilinx vertex FPGA validates the new strategy.