Title :
Low-voltage limitations and challenges of memory-rich nano-scale CMOS LSIs
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
Abstract :
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k bulk) that can reduce VT variations.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; MOSFET; SRAM chips; large scale integration; logic gates; low-power electronics; nanoelectronics; DRAM sense amplifiers; MOSFET; SRAM cells; logic gates; low-voltage limitations; memory-rich nanoscale CMOS LSI; repair techniques; threshold voltage variation; CMOS logic circuits; Flip-flops; Logic circuits; Logic devices; Logic gates; MOSFETs; RNA; Random access memory; Read-write memory; Threshold voltage;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734991
