Interconnect and package design of a heterogeneous stacked-silicon FPGA

This paper reviews the interconnect and package design of a heterogeneous stacked-silicon FPGA. Up to five dice from two die types are mounted on a passive silicon interposer. A hardware- and software-scalable FPGA family can be created by mixing different combinations of these two die types. The FPGA, inside a low-temperature co-fired ceramic (LTCC) package, consists of two silicon die types - up to three FPGA ICs having a total of seventy-two 13.1-Gb/s transceivers (943.2 Gb/s full-duplex) and up to two GTZ ICs having up to sixteen 28.05-Gb/s transceivers (448.8 Gb/s full-duplex). Two types of interconnects are discussed: those joining the ICs through wires in the silicon interposer, and those connecting the 28-Gb/s transceivers through TSVs in the interposer to the package balls. An end-to-end 28.05-Gb/s channel simulation is discussed in the context of silicon interposer resistivity as well as package material and stack-up. In addition, this paper reviews 3D thermal-mechanical analysis confirming the reliability of heterogeneous stacked silicon.