Critical path delay and leakage power reduction during test in deep submicron IC´s

This paper reviews leakage current mechanisms and optimization of stand-by leakage power for different test input patterns of VLSI circuits and critical path delay reduction during test and burn-in for nanometer technologies. The need for low power has caused a major paradigm shift where power dissipation has become an important consideration for performance and area. High leakage power dissipation in stand-by digital circuits is becoming a major problem in deep-sub micrometer technology. The nonlinear-objective function of the leakage power can be approximated to finite element model thereby the problem can be solved efficiently. Control point insertion of tristate gates is used as a fault free or error free circuit but occupies area and increases the delay. An efficient technique is proposed for Critical Path Delay minimization using tristate gates. An experimental result on the IEEE ISCAS´89 benchmark circuits is analyzed in Xilinx FPGA