Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates

Serial link transceivers with sophisticated equalization are needed for data transmission over high-loss electrical channels such as backplanes. This paper highlights design techniques for extending the data rates of such circuits by describing a 28-Gb/s transceiver implemented in 32-nm SOI CMOS technology. Equalization is provided by a 4-tap feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier with active feedback topology and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology with double the speed of previous designs. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated over a 35-dB loss channel with a power consumption of 693 mW/lane.